V*****

V*****

 

Research Engineer

 

  • Contract
  • USA Work Ready
  • Research Engineer

  • Wireless communication enginee

  • FPGA design engineer

  • Job Posted: Tuesday, March 17, 2015

  • Expires On: Monday, August 04, 2014

  • Job Type: Contract

  • Duration: Negotiable

  • Desired Salary: $60.00/hr

  • Work Authorization: EAD

I am a research engineer at IRISA, France. I am working on wireless protocols development, integration, and validation.
I have more than 5 years working experience of digital signal processing for wireless communication.
For past 2 years, I am working in VHDL design, and testing it using different simulation tools. I have experience of working Matlab, C/C++, Python, and some high level synthesis (HLS) tools e.g. CatapultC, Vivado HLS.
During my current two jobs, I have been developing a flexible software defined radio using Nutaq-Perseus6010 a Xilinx V-6 based FPGA platform. I am also familiar with ML-605, and USRP1 and 2.

I also have been working on USRP1 for 3 years, where I developed a working SDR test-bed and performed a diversity analysis for 2x1 relayed in artificially created Rayleigh fading environment in indoor, and nobody area scenarios. Moreover, I have a strong working skills in Matlab.

I am fluent in English, and intermediate in French.

 
  • Brussels, BU, Belgium

  • Bordeaux, AQ, France

  • Frankfurt, HE, Germany

  • Luxembourg, LU, Luxembourg

  • Amsterdam, NH, Netherlands

  • Stockholm, ST, Sweden

  • London, EN, United Kingdom

  • Lyon, RH, France

  • Copenhagen , SK, Denmark